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delphi dnm, non-isolated point of load dc/dc power modules: 2.8- 5.5v in, 0. 75-3.3v/10a out the delphi serie s dnm 04, 2.8-5.5v input, singl e output, non -i solate d point of loa d dc/dc co nverters a r e the latest of f e ring f r om a worl d leade r in po wer system and technolo g y and man u facturi ng -- delt a electro n ics, inc. the dnm04 seri es provide s a p r og ramm able outpu t volt age from 0.75v to 3.3v using an e x ternal re sist or . the dnm serie s has flexible and program mable tr a cki ng and sequ enci ng features to enabl e a variety of st artup volt ages a s well as sequ enci ng and tracking betwe en po wer mod u les. this p r od uct family is available in a su rface mount or sip p a ckag e an d provide s u p to 10a of current in an indu stry st an dard foot print. with creative de sign techn o logy and o p timizat i on o f comp one nt placem ent, these conve r te rs p o sse s s o u t s t a ndin g el ectri c al and therm a l perform an ce and extre m ely high re liability under highl y stre ssful ope rating co nditio n s. options negative on/ o f f logic t r acking feature smd p a ckage applica t ions t e lecom/dat a co m distributed po w e r architectures servers and w o r kst ations lan/w a n applications dat a processing applications feat ure s high ef ficiency : 9 6% @ 5.0v in, 3. 3v/10a out small size and low p r ofile: (sip) 50.8x 1 3 .4x 8.0 mm (2.00? x 0. 53 ? x 0.3 1 ?) signle-in-line (sip) p a ckaging s t andard footp r in t v o lt age and resistor-based t r im pre-bias st artup output volt age t r acking no minimum load required output volt age pr ogrammable f r o m 0.75vdc to 3.3vd c via external res i stor fixed f r equenc y operation input uvl o , out put otp , ocp r e m o t e o n /o ff remote sense iso 9001, t l 90 00, iso 14 001, qs9000, o h sas1800 1 certified manufactu r ing facility ul/cul 60950 ( u s & canada ) r e cognized, and tuv (en 609 50) ce rtified ce mark meet s 73/23/eec and 9 3 /68/eec directives d a t a s h eet ds_dnm 04si p 10_ 05 292 00 6 delt a elec tronics , inc .
ds_dnm 04s ip10_052 920 06 2 technical specifica t i o ns (t a = 25 c, airfl o w rate = 300 lf m, v in = 2.8vdc and 5.5v dc, n o m inal v o u t u n le ss ot her w ise no ted.) p a ramete r notes an d co nditio n s dnm 04s0a0 r 10pf a m i n . t y p . max . unit s absolute ma ximum ra tings inpu t v o lt ag e (con ti nuous) 0 5.8 vdc t r acking v o l t age v i n,max vdc operati ng t e mpera t ure refer to figure 45 for mea s uring poin t -40 +125 c s t orage t e mperatu r e -55 +125 c i n put characteri s ti cs operati ng inpu t v o l t age v out Q vi n ? 0. 5 2.8 5.5 v inpu t under -v ol t a g e lo cko ut t u rn-on v o l t age th reshold 2.2 v t u rn-o f f v o lt age th reshold 2.0 v max i mu m i npu t current v i n=2.8v to 5 . 5v , io=io,max 10 a no-load inpu t curr ent 70 100 ma of f conv erter inpu t current 20 30 m a inru sh t r an sient v i n=2.8v to 5 . 5v , io=io,min to io,max 0.1 a 2 s recommended ino u t fu se 15 a output charac t eri s ti cs outpu t v o lt age set point v i n=5v , io=100 % io, max , t c =25 -2.0 vo , s e t +2. 0 % v o ,se t outpu t v o lt age adj u st able range 0.7525 3.63 v outpu t v o lt age reg u lation ov er line v i n=2 . 8v to 5 . 5v 0.3 % v o ,se t ov er load io= i o , m i n to io ,m a x 0.4 % v o ,se t ov er t e mperature t c =-40 to 100 0 . 8 % v o ,se t t o t a l ou tpu t v o lt ag e range ov er sample lo ad, l i ne and temperatur e -3.0 +3. 0 % v o ,se t outpu t v o lt age rip p le and noise 5hz to 20mhz ban dw id th peak- t o-pe ak full load , 1f cer a mic, 10f t a nt alum 25 50 mv rms full load , 1f cer a mic, 10f t a nt alum 8 15 mv outpu t cur r ent ran ge 0 10 a outpu t v o lt age ov e r-shoo t at s t ar t-up 5 % v o ,se t outpu t dc cur r ent- l imit in ception 220 280 % io outpu t shor t-circu i t curre nt (hiccup m ode) i o ,s/ c 3.5 adc dynami c chara cteri s ti cs dy namic load response 10f t an & 1f ce ramic load cap , 2.5 a /s posi tiv e s t ep chan ge in ou tput curre nt 50% io, max to 100 % io, max 200 300 mv negativ e s t ep cha nge in ou tpu t curr ent 100% io , max to 50 % io, max 200 300 mv setting t i me to 10 % o f pe ak dev i t a tio n 25 s t u rn-on t r an sien t io= i o . m a x s t a r t - up t i m e , f r om o n /o f f co nt r o l v i n = v i n , m i n, v o = 1 0% of v o ,s et 4 6 m s s t art-u p t i m e , f r o m inpu t v o =10% of v o ,se t 4 6 ms outpu t v o lt age ri se t i me t i me fo r v o to ri se from 10% to 90 % o f v o ,set 4 8 ms max i mu m outpu t s t artup cap a ci tiv e l oad full load ; e s r R 1m ? 1000 f full load ; e s r R 10 m ? 5 0 0 0 f effi ci ency vo = 3 . 3 v v i =5v , 100% load 96.0 % v o =2.5 v v i =5v , 100% load 9 4 . 2 % vo = 1 . 8 v v i =5v , 100% load 92.4 % v o =1.5 v v i =5v , 100% load 9 1 . 4 % vo = 1 . 2 v v i =5v , 100% load 90.0 % v o =0.7 5 v v i =5v , 100% load 8 6 . 3 % fea t ure chara cteri s ti cs sw itching freq uen cy 300 kh z on/off control, ( n egativ e logic) logic low v o lt a g e module on , v o n / o f f -0.2 0.3 v logic high v o lt age module o f f, v o n/o f f 1.5 v i n,max v logic low current module on , ion / o f f 10 a logic high cur r ent module o f f, ion / o f f 0.2 1 ma on/off control, ( p osi t iv e logic) logic high v o lt age module on , v o n / o f f v i n,max v logic low v o lt a g e module o f f, v o n/o f f -0.2 0.3 v logic low current module on , ion / o f f 0.2 1 ma logic high cur r ent module o f f, ion / o f f 10 a t r acking slew rate cap ability 0.1 2 v/mse c t r acking delay t i me delay from v i n . min to a pplicatio n o f tra cki ng v o lt age 10 ms t r ac king a c cura cy pow e r-up 2v /ms 100 200 mv pow e r-do w n 1v /ms 200 400 mv remote se nse ran ge 0.1 v general specif ica t ions mtbf io=100% of io, max ; t a =25 c 21.91 m hour s w e igh t 1 0 g r a m s ov er-t emperature shut dow n refer to figure 45 for mea s uring poin t 130 c
ds_dnm 04s ip10_052 920 06 3 electri cal characteristi cs cur ves figure 1 : converter ef ficie n c y vs. output current (3.3v out) figure 2 : converter ef ficie n c y vs. output current (2.5v out) figure 3 : converter ef ficie n c y vs. output current (1.8v out) figure 4 : converter ef ficie n c y vs. output current (1.5v out) figure 5 : converter ef ficie n c y vs. output current (1.2v out) figure 6 : converter ef ficie n c y vs. output current (0.75v o u t) 75 80 85 90 95 100 123456789 1 0 out p ur c u r r e nt (a ) efficiency(%) v i n=5. 0v v i n=4. 5v v i n=5. 5v 75 80 85 90 95 100 12345 6789 1 0 out p ur c u r r e n t (a ) efficiency(%) v in= 5 .0 v i n=3. 0v v i n=5. 5v 75 80 85 90 95 100 123456789 1 0 out p ur c u r r e nt (a ) efficiency(%) v i n=5. 0v v i n=2. 8v v i n=5. 5v 75 80 85 90 95 100 123456789 1 0 o u t p u r cu rren t (a ) efficiency(%) v in= 5 .0 v i n=2. 8v v i n=5. 5v 60 65 70 75 80 85 90 95 12 34 56 78 9 1 0 o u t p u r cu rren t (a ) efficiency(%) v in= 5 .0 v i n=2. 8v v i n=5. 5v 65 70 75 80 85 90 95 12 34 56 78 9 1 0 out p ur c u r r e n t (a ) efficiency(%) v in= 5 .0 v i n=2. 8v v i n=5. 5v
ds_dnm 04s ip10_052 920 06 4 electri cal characteristi cs cur ves figure 7 : outp ut rippl e & nois e at 3.3v in, 2.5 v /10a o u t figure 8 : outp ut rippl e & nois e at 3.3v in, 1.8 v /10a o u t figure 9 : outp ut rippl e & nois e at 5v in, 3.3v/ 10a o u t figure 1 0 : output ripp le & no i s e at 5v in, 1.8 v /10a o u t figure 1 1 : t u rn on de lay ti me at 3.3v in, 2.5v /10a o u t figure 1 2 : t u rn on de lay ti me at 3.3v in, 1.8v /10a o u t
ds_dnm 04s ip10_052 920 06 5 electri cal characteristi cs cur ves figure 1 3 : t u rn on de lay ti me at 5v in, 3.3v/1 0a out figure 1 4 : t u rn on de lay ti me at 5v in, 1.8v/1 0a out figure 1 5 : t u rn on del ay time at remote turn on 5vi n , 3.3v/16a ou t figure 1 6 : t u rn on del ay time at remote tur n on 3.3vin, 2 . 5 v/16a out figure 1 7 : t u rn on d e lay ti me at remote turn on w i th e x ternal capac itors (co = 5000 f ) 5vi n , 3.3v/16a o u t figure 1 8 : t u rn on delay tim e at remo te turn on with external capac itors (co = 5000 f ) 3.3 v in, 2.5v/16 a out
ds_dnm 04s ip10_052 920 06 6 electri cal characteristi cs cur ves figure 1 9 : t y p i cal trans ient re spons e to step loa d cha nge at 2.5a/ s from 1 00% to 50 % of io, max at 5v i n , 3.3v out (cout = 1uf ce ramic, 10 f t a nt alu m ) figure 2 0 : t y p i cal trans ient re spons e to step loa d cha nge at 2.5a/ s from 5 0 % to 100 % of io, max at 5v i n , 3.3v out (cout = 1uf cer a mic, 10 f t a n t a l u m ) figure 2 1 : t y p i cal trans ient re spons e to step loa d cha nge at 2.5a/ s from 1 00% to 5 0 % of io, max at 5v i n , 1.8v o u t (cout = 1uf cer a mic, 10 f t a nt a l um ) figure 2 2 : t y pical trans ie nt response to step loa d cha nge at 2.5a/ s from 5 0 % to 100 % of io, max at 5v i n , 1.8v o u t (cout = 1uf ce ramic, 10 f t a nt alu m )
ds_dnm 04s ip10_052 920 06 7 electri cal characteristi cs cur ves figure 2 3 : t y p i cal trans ient re spons e to step loa d cha nge at 2.5a/ s fro m 100 % to 5 0 % of io, max at 3.3v i n , 2.5v o u t (co u t = 1uf ceramic , 10 f t ant alu m ) figure 2 4 : t y pical trans ient re spons e to step loa d cha nge at 2.5a/ s from 50% to 1 0 0 % of io, max at 3.3v in, 2.5v o u t (co u t = 1uf ceramic , 10 f t ant alu m ) figure 2 5 : t y p i cal trans ient re spons e to step loa d cha nge at 2.5a/ s fro m 100 % to 5 0 % of io, max at 3.3v i n , 1.8v o u t (co u t = 1uf ceramic , 10 f t ant alu m ) figure 2 6 : t y pical trans ient re spons e to step loa d cha nge at 2.5a/ s from 50% to 1 0 0 % of io, max at 3.3v in, 1.8v o u t (co u t = 1uf cerami c, 10 f t ant alu m ) figure 2 7 : output short circuit current 5v i n , 0.75v o u t figure 2 8 : t u rn on w i th prebia s 5vin, 3.3v/0 a out, vbias = 1 .0vdc
ds_dnm 04s ip10_052 920 06 8 test configura t ions v i (+) v i (-) battery 2 100uf tantalum l to oscilloscope note: input reflected -ri ppl e current is measured with a s i mu la ted sou r ce in du c t an c e . c u rr en t is me as ur ed a t the input of the module. figure 2 9 : input reflected-ri p p le test setup vo gnd copper strip 10uf tantalum 1uf ceramic scope resistive load note: use a 10 f t ant alu m and 1 f cap a cito r . sco pe measurement shoul d be m ade u s ing a b nc cabl e. figure 3 0 : peak-p eak o u tp ut nois e an d st artup transi ent me asur e m ent test setup. su ppl y i i v i vo gnd io lo a d co n t act an d dis t r i but i on l o ss es co n t act re si st an ce vo vi n figure 3 1 : output volt ag e a nd ef fic i ency me asur e m ent test setup note: all m easure m ent s are t a ken at the mo dule terminal s. when the mo d u le is not sol dere d (via so cket), pla c e kelvin co nne ction s at module terminal s to avoid measu r eme n t erro rs due to cont act resi st ance. % 100 ) ( = ii vi io vo design considerations input source impedance to maintai n l o w n o ise an d ripple at the input voltage, it is critical to use low esr cap a cito rs at the input to the module. figu re 32 sho w s the input rippl e voltage (mvp-p ) for variou s o u tput model s using 20 0 f(2 x100u f) low esr tantalum cap a cito r (ke m et p/n: t491d1 07m0 16a s, avx p/n: tajd107m 106r, or equi valent) in parallel with 47 f cer a mi c ca pacit o r (tdk p/n:c5 7 50x7r1c476 m o r equivalent ). figure 33 sh ows much lower in put voltage ripple whe n input ca pa cita nce i s increa sed to 40 0 f (4 x 100 f) tantalum capa citors in pa rallel with 94 f (2 x 47 f) ce rami c c apa cit o r. the input cap a citan c e sho u ld be abl e to handle a n ac ripple cu rre nt of at least: figure 3 3 : input voltage ri pp l e for various o u tput mode ls, io = 10 a (cin = 4 100 f tanta l u m // 2 47 f c e ra mic) 0 50 100 150 200 012 34 o u t put v ol t a ge ( v d c ) input ripple voltage (mvp-p) 5.0v i n 3.3v i n figure 3 2 : inp u t voltage rip p l e for various o u tput mo de ls, io = 10 a (cin = 2 100 f tanta l u m // 47 f cer a mic) 0 50 100 150 200 250 300 350 012 34 o u t put v ol t a ge ( v d c ) input ripple voltage (mvp-p) 5.0v i n 3.3v i n arms vin vout vin vout iout irms ? ? ? ? ? ? ? = 1
ds_dnm 04s ip10_052 920 06 9 vo vi n on /off gnd rpul l - up rl i on/of f figure 3 5 : negative re mote on/of f imple m ent atio n over-current protection t o provide prote c tion in an outp u t over loa d fa ult con d ition, the unit is equi p ped with i n ternal over-current prote c tion. whe n the over-curre nt prote c tio n is trigge red, th e unit enters hiccu p m ode. the u n it s operate no rm ally once the fault conditio n is rem o ved. design considera t ions (con.) the po we r module sh ou ld be conn e c ted to a lo w ac-i mpe dan ce input so urce. hig h ly inductive source impeda nces can af fe ct the st ability of the module. an input ca p a cit ance must be placed clo s e to the modules input pin s to filter ripple curre n t and ensure m odu le st ability in the pre s en ce o f inductive trace s that supp ly the input volt age to the mo dule. safet y considerations for safety-a g ency a p p r ova l the po we r m odule mu st b e inst all ed in co mplian c e with the sp a c ing and se p a ratio n requi rem ent s of the end-u s e safety agen cy st an da rds. for the co nverter o u tput to be con s id ered meeting t he requi rem ent s of safety ex tra-lo w volt a g e (sel v ) , the input must meet sel v requireme nt s. the po wer module ha s extra-lo w volt age (e l v ) o u t put s whe n a l l input s are e l v . the inp u t to these unit s is to be provided with a maximum 15 a time-delay fuse in the u n g rou nde d lea d . fea t ures descriptions remote on/of f the dnm/dnl se rie s po wer mo dule s have an on/of f pin for rem o te on/of f operation. b o th po sitive and negative on /off logic options a r e available in the dnm/ d nl se ries p o wer m odule s . for p o sitive logic modul e , conn ect an open coll ector (np n ) tra n si stor o r op en drain (n ch annel ) mos f et betwe en the on/of f pin and the gnd pi n (se e figure 34). positive logi c on/off sign a l turns th e m odule on d u ring the logi c high and turns th e module off durin g the lo g i c low. wh en th e positive on/ o f f function is not used, le a v e the pin floatin g or tie to v i n (modul e will be on). for ne gative logic m odule, the on/off pin is pulle d hi gh with an external pull-up re sist or (s e e figu r e 3 5 ) . n e gative logic on/off sign al turns the module o ff during lo gic high a nd tu rn s the m odul e on duri ng l ogic l o w. if the negative on/ o f f function is not u s ed, leave the pin floating or tie to gnd. (m odule will be on) rl vo vi n o n /off gn d i on/ o f f figure 3 4 : positive rem o te on/of f im plem ent a tion
ds_dnm 04s ip10_052 920 06 10 v o ( v ) v tr im ( v ) 0. 752 5 op en 1. 2 0 . 6 2 4 1. 5 0 . 5 7 3 1. 8 0 . 5 2 2 2. 5 0 . 4 0 3 3. 3 0 . 2 6 7 v o (v) r t r im (k ? ) 0. 752 5 op e n 1. 2 41. 97 1. 5 23. 08 1. 8 15. 00 2. 5 6 . 9 5 3. 3 3 . 1 6 t a ble 2 vo tr im gnd rl oa d vt r i m + _ figure 3 8 : circuit confi gurati on for progr a m mi ng o u tput vol t age usin g extern al volt ag e source t able 1 provi des rt rim values requi red for some co mmon output volt ag es, whil e t able 2 provid e s value of e x ternal volt age source, vtrim, for the sam e comm on outpu t volt age s. by usin g a 1 % tolera nce trim resisto r , set point toleran c e of 2% can b e achi eved as spe c ified in the electri c al spe c ificatio n. t a ble 1 vo tr i m gnd rlo a d rt ri m figure 3 7 : circuit config urati on for progr a m mi ng o u tput vol t age usin g an exter nal res i stor 7525 . 0 1698 . 0 7 . 0 u vo vtrim for exampl e , to program the output volt age of a dnl module to 3.3 vdc, vtrim is calculated a s follows v vtrim 267 . 0 7525 . 0 3 . 3 1698 . 0 7 . 0 u : : ? ? o ? ? a k rtrim 15 5110 7525 . 0 8 . 1 21070 dnl ca n al so be p r og rammed by apply a volt age betwe en the trim an d gnd pin s (figure 38 ). the followin g equ ation can b e use d to determine the valu e of vtrim neede d for a desi r ed output volt ag e v o : : ? ? o ? ? a 5110 7525 . 0 21070 vo rtrim for exa m ple, to pro g ram t he outp u t vol t age of th e dnl module to 1.8 v dc, rtrim i s cal c ulate d as follows: fea t ures descriptions (con.) over-t emperature protection the over-tem peratu r e p r ot ection con s i s ts of circuitry that provide s protection fro m thermal damag e. if the temperature excee d s the ove r-tem pe ra ture thre sh old the module will shut down. th e module will try to restart after shutdown. if the over-tem perature condition still exi s t s durin g re start, the module will shut d o wn ag ain. this resta r t trial will continue u n til the temp eratu r e is wit h in specification remote sense the dnm/ dnl p r ovide v o rem o te sensi ng to a c hieve prop er regul a t ion at the load point s and redu ce ef fect s of distrib u tion lo sses on outp u t li ne. in the event of an o pen remote se nse line, the mod u le shall mai n t a in local sense regul ation through a n internal re sisto r . the mod u le shall corre c t for a t o t a l of 0.5v o f loss. t he re mote sen s e li ne impeda nce shall be < 1 0 : . vo se ns e vin gnd rl dis t ribution los s es d i stribution losses distributi on l di stribution figure 3 6 : ef fective circuit co nfigur ation for r e mote sens e oper ation o u t p u t v o l t a g e p r o g r a m m i n g the output volt age of the dnm/ d nl ca n be prog ram m ed to any volt age betwee n 0.75vdc and 3.3vd c b y con n e c ting o ne re sisto r (sho wn a s rtrim in figure 37) betwe en the trim and g nd pin s of the module. wi thout this external resi stor , the o u tput volt age of the mod u l e is 0.7525 vd c. t o cal c ulate t he value of the resi stor rtrim for a p a rti c ular outp u t volt age v o , please u s e the followin g equ ation:
ds_dnm 04s ip10_052 920 06 11 the dnl fami ly has 3 different option co des fo r t r ack function. option co de a: the outp u t voltage tra c k cha r a c teri stic can be a c hi e v ed whe n the output voltage of ps2 follows the output voltag e of ps1 on a volt-to-volt basi s . (fig ure 41) option co de b: no tra c k function option co de c: implem e n tation of ad vance d po wer tracking tech nique s is based on conn e c ting the power good signal or sele ctin g prop er va lue for external resi sto r r1 (f igure 4 0 to figure 4 3 ). figure 4 0 : seque ntial figure 4 1 : simultan eo us figure 4 2 : ratio-m e tric figure 4 3 : ratio-m e tric fea t ure descriptions (con.) the am ount of powe r d e livered by the module i s the volt age at the output terminals multiplie d by the outp u t curre n t. whe n usin g the tri m feature, the output volt a ge of the modul e can b e increa sed, which at the sa me output cu rren t would in cre a se the p o wer output of the module. ca re sh ould be t a ke n to e n su re th at the maximum out put power of the module must not exceed the maximum rated po we r ( v o .set x io.max p m a x ) . v o lt age margining output volt age margi n ing can be impl emented in the dnl modul e s by conn ecti ng a resi sto r , r m a rgin -u p , from the t r im pi n to the grou nd pin for m a rgini n g - up t he output volt ag e and by con nectin g a re sistor , r ma rgin -d o w n , from the t r i m pin to the ou tput pin for m a rgini n g - do wn . figure 39 shows the circuit configu r ation for output volt age margining. if u nused, leave the trim pin unconn ecte d. a cal c ulatio n tool is ava ilable from t h e evaluation proce dure which co m pute s t he value s of r m a rgin -u p and r ma rgin -d o w n for a spe c ific out put volt age a nd margi n perce nt age. vo on / o ff vin gnd tr i m q2 q1 rm argi n-u p rm argi n-do wn rt r i m figure 3 9 : circuit config urati on for outp u t voltag e margi n i ng voltage tracking the dnm/ d nl family was desi gne d for appli c ation s that have outp u t volt age tracking req u i r eme n t s du ring power-up a n d powe r -do w n. the devices have a tra c k pin to impl e m ent thre e types of tra cki ng m e tho d : seq uential, ratio-metri c and sim u lt a neou s. tra c k simplifie s the t a sk of suppl y volt age tra c king i n a p o wer system by en abling mo dul es to track ea ch othe r , or a n y external volt a ge, durin g po wer-u p and p o we r-do wn. by conn ectin g multiple m odule s tog e ther , cu stome r s can get multi p le mo dule s to track thei r output volt ag es to the volt age applied o n the track pin. the dnl fam ily has 3 different option co des for t r a c k function ps1 ps1 ps1 ps2 ps2 ps1 ps1 ps2 ps2 ps2 ps2 ps1 ps1 ps2 ps2 -v -v ps1
ds_dnm 04s ip10_052 920 06 12 fea t ure descriptions (con. ) sequential sequential st art-u p (fig u r e 40 ) is impleme n ted by con n e c ting th e power go o d pin of ps1 to the track pin of ps2 with a re sisto r ? c a p a c itor (rc) circuit. sugg est to use 1 f ce rami c ca p a ci tor and 2k ? resi stor here. beside s, this config uratio n requi re s ps1 to have a powe r good fun c tion . ratio-metri c ratio?m etri c is impleme n ted by selecting the resi stor values of the voltage divide r on th e t r a c k pin. t o si mplify the trackin g d e sig n , set initial value of r2 equal to 20k ? at internal circu i t and adju s t resi stor r1 for the different tracking m e th od. the ci rcui t diagram of ratio-metri c is the same a s simultaneo us when vo ps2 tracks the vo ps1 . for ratio-met r ic a ppli c ation s that ne ed th e output s of ps1 and ps2 go to the regulat ion set point at the same time (figu r e 43 ), use the followi ng equation (1) to calcul ate the value of resi stor r1, set ? v= vo set,ps1 ?vo set,p s2 and ? v will be negative. ? ? ? + = k vref vref v vo r ps set 20 * ] ) [( 1 2 , ---- -- -- -- -- -- ( 1 ) note: 1. vref =0.4 vo set,ps2 2. ? v is the m a ximum differen c e of voltage bet wee n ps1 and ps2 supply voltag e. for ratio-m e tric appli c atio ns that nee d the ps2 supply voltage ri se s first at po we r up an d falls se con d at p o we r down (figu r e 42), use the following equation (2) to cal c ulate the value of resi stor r1, set ? v 0.4 vo set,ps 2 and ? v will be negative. ? ? ? ? = k vref vref v vo r ps set 20 * ] ) [( 1 2 , -- -- -- -- -- -- -- -- -- (2) note: 1. vref =0.4 vo set,ps2 ? v is define d as the volt a ge dif f eren ce betwe en v o ps 1 and vo ps2 when v o ps2 reache s it s rate d volt a ge. r tr a c k vo ps 1 ps2 vo ps2 ps 1 vi n vi n pw r g d en abl e en abl e c simultaneous simult ane ou s tracki ng (fi gure 4 1 ) is i m pleme n ted by usin g a volt age divider arou nd the track pin. the obje c tive is to minimize the volt age dif f eren ce bet we en the power su pply output s durin g po wer up and d o wn. for type a (dnx0a0xxxx a ), the simult aneo us tracki ng can be a c co mplish ed by conne cting v o ps1 to the trac k pin of ps2 where the volt a ge divider i s insid e the ps2. tr a c k vo ps 1 ps 2 vo ps 2 ps 1 vi n vi n en abl e en abl e for type c (dnx0a0xxxx c ), the si mult aneo us tracki ng can b e acco mplish ed by putting r1 e qual to 30.1 k throug h v o ps1 to the track pin of ps2. r1 r2 tr a c k vo ps 1 ??? vo ps 2 ps 1 vi n vi n en ab l e en abl e to t r ac k i ng ci rcu i t 20 k 30 . 1 k
ds_dnm 04s ip10_052 920 06 13 thermal consi d era t i o ns therm a l man ageme n t is a n importa nt part of the syst em desi gn. to e n su re p r op er, reliabl e ope ration, suffici e n t cooli ng of th e po we r mod u le is nee de d over th e e n tire temperature range of the modul e. co n v ection co olin g is usu a lly the dominant mo d e of heat tran sfer. hen c e, the choi ce of eq uipment to chara c te rize the thermal p e rf orma nce of the po wer m odule i s a wind tunnel. thermal t esting setup delta? s dc/ dc po we r module s are chara c te rize d in heated verti c al wind tunn els t hat simu late the thermal environ ment s encou ntered in most electroni cs equipm ent. this type of equipm ent comm only u s e s vertically mou n ted circuit card s in cabi n e t rac ks in w h ich the power mo dule s are m o unted. the followi ng figure shows the wind tunne l cha r a c teri zati on setup. th e powe r mod u le is mount ed on a test pwb and is vertically po sitioned within the wind tun nel. the hei ght of this fan du ct is co nst antly kept at 25.4mm (1? ? ). thermal derating heat can be removed by in cre a si ng airflow ove r the module. to enhan ce system relia bi lity, the power module shoul d always be operated bel ow the maximum operating te mperature. if the tempe r a t ure ex ceed s the maximum module temperat ure, reliability of the unit m a y be affected. n o t e : w i n d tu n n e l t e s t s e t u p f i g u r e d i m e ns i o n s a r e i n m i l l i m e t e r s a n d ( i nc he s ) m o dule a ir f l o w 12. 7 (0. 5 ?) 50. 8 ( 2. 0? ) fa c i ng p w b pw b a i r ve l o cit y an d amb i en t t e m p e r at ure m e as ure d be lo w t h e m o dule 25. 4 (1. 0 ?) figure 4 4 : w i nd tunne l test setup
ds_dnm 04s ip10_052 920 06 14 thermal cur ves figure 4 5 : t e mp eratur e mea s ure m e n t locati on * t he allow e d max i mu m hot s pot temperatur e is define d at 125 d n m 04s0 a 0r 10( stand ar d) o u tput cur r ent v s . a m bi ent tem per atur e and a i r v e l o c i t y @ vi n = 5 v , vo = 3.3v ( e ither o r i entation ) 0 2 4 6 8 10 12 60 65 70 7 5 80 85 a m b i ent tem p er atur e ( ) o u tpu t cu rr en t( a ) natural con v ec t i on figure 4 6 : dnm04s0a 0r1 0 (s t andar d) output current vs. ambi ent tempe r ature an d air v e locity@ v in= 5 v , v o = 3 .3v(either orient atio n) d n m 04s0 a 0r 10( stand ar d) o u tput cur r ent v s . a m bi ent tem per atur e and a i r v e l o c i t y @ vi n = 5.0v, vo = 0.75 v ( e ithe r o r i entati on) 0 2 4 6 8 10 12 60 65 70 7 5 80 85 a m b i ent temp er atur e ( ) o u tpu t cu rr en t( a ) natural conv ec ti on figure 4 7 : dnm04s0a 0r1 0 ( s t andar d) outp ut current vs. ambi ent tempe r ature an d air v e locity@ v in= 5 v , v o = 0 .75v(ei t her orient atio n) d n m 04s 0a 0 r 10 (s t andar d) ou t put cur r ent v s . a m bient temper at ur e and a i r v e l o cit y @ v i n = 3 . 3v , v o = 2. 5v (e it her orient at ion) 0 2 4 6 8 10 12 60 65 70 75 80 85 am b i ent t e m per at ur e ( ) o u t put c u rrent (a) na t u r a l co nv ec t i on figure 4 8 : dnm04s0a 0r1 0 (s t andar d) output current vs. ambi ent tempe r ature an d air v e locity@ v in= 5 v , v o = 2 .5v(eithe r orient atio n) d n m0 4s 0a 0 r 1 0 (s t and ard) out put c u r r ent v s . a m bien t te mpera t ure and a i r v e locit y @ v i n = 3. 3v , v o = 0. 75v (e it he r or ient at ion) 0 2 4 6 8 10 12 60 65 7 0 75 80 85 ambie n t t e mpera t ure ( ) o u t put c u rr ent( a ) na tu r a l c onv e c t i on figure 4 9 : dnm04s0a 0r1 0 (s t andar d) output current vs. ambi ent tempe r ature an d air v e locity@ v i n= 5 v , v o = 0 .75v(e ith e r orient atio n)
ds_dnm 04s ip10_052 920 06 15 mechanical dra w ing smd p a ck age ( o pti o nal) sip p a c k a g e
ds_dnm 04s ip10_052 920 06 16 p a rt numbering system d n m 0 4 s 0 a 0 r 1 0 p f a produc t series in p u t v o lt ag e nu mb ers o f outp ut s outp ut v o lt ag e pack ag e ty p e outp ut current on/off lo gic o p t i o n co d e dnl - 1 6 a dnm - 10a dns - 6a 04 - 2.8~5.5v 12 - 9~14v s - single 0a0 - programma ble r - sip s - smd 10 - 10a n- negative p- positive f- ro hs 6/6 (lead f r ee ) a - s t anda rd fun c tion: sequencing b - no tracking pi n c - t r acking feat ure model list model name packaging input v o lt ag e outpu t v o lt a g e outpu t cu rr ent efficiency 5.0v in, 100 % load dnm04s0a0r 10 pf a sip 2.8 ~ 5.5vdc 0.75 v~ 3.3vdc 10a 96.0% ( 3 .3v) dnm04s0a0s10 pf a smd 2.8 ~ 5.5vdc 0.75 v~ 3.3vdc 10a 96.0% ( 3 .3v) c o nt ac t : www .delt a . com.tw/dcd c us a : t e lepho ne: east coast: (888) 33 5 82 01 w e st coast: (888) 33 5 82 08 f a x: (97 8 ) 656 396 4 email: dcd c @ delt a -c orp.co m europe : phon e: + 41 31 998 5 3 1 1 f a x: + 41 31 9 9 8 53 53 email: dcdc@delt a - e s.com a s i a & the re st of w o r l d: t e lepho ne: + 8 86 3 45 26 10 7 ext 6 220 f a x: + 886 3 4 5 134 85 email: dcd c @ delt a .com.t w w arra nt y delt a of fers a two (2) year limited warran ty . complete warra n ty information is liste d on our web site or is available upo n requ est from delt a. information fu rnished by delt a is b e lieve d to be accu rate and reliab l e. however , no re sp on sibi lity is assume d by delt a for it s u s e, n o r for a n y infrin gement s of p a tent s or oth e r rig h t s of third p a rties, whi c h may result from it s use. no li cen s e is g r anted by implicatio n o r otherwise un der any p a ten t or p a t ent ri g h t s of delt a. delt a re se rve s the right to revise the s e spe c ification s at any time, without noti c e .

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